G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 7/52 (2006.01)
Patent
CA 2294554
A multiplier circuit for use with large numbers is presented. The circuit accepts two large numbers and segments the second number into a number of segments each of a known size. The unsegmented number is multiplied using Booth Encoding by the lowest order segment to form two partial products which are added to form a partial product and an associated carry value. The partial product is shifted right one segment and the result is padded. The next segment is then multiplied by the unsegmented number using Booth Encoding to provide two further partial products for summation. Summation of the three values results in a partial product and an associated carry value. And so the process is iterated until all segments have been multiplied by the unsegmented number. Padding of each partial product is performed based on a flag which is set when a negative encoded number is generated by the Booth Encoding and when a carry out from the sum is not fully resolved. When the flag is not set, the padding is with zeros; when the flag is set, the padding is with ones.
Amer Maher
Fasken Martineau Dumoulin Llp
Mosaid Technologies Incorporated
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