Method and composition of matter for improving conductor...

H - Electricity – 05 – K

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356/142, 96/166

H05K 3/06 (2006.01) G03F 7/09 (2006.01) H01L 21/027 (2006.01) H01L 21/312 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1255142

Abstract of the Disclosure A method which provides for a permanent planarization layer on a multilayer integrated circuit. The planarization layer resides above other circuit layers which reflect incident light. A layer of photoresist is formed over the planarization layers and imaged through a mask with circuit defining structure. During exposure of the photoresist, incident light passes through the planarization layer. Scattering from the boundary of the planarization layer and photoresist is minimized because the index of refraction of the planarization layer is substantially equal to the index of refraction of the photoresist. Light reflected from the underlying layers is substantially absorbed by the planarization layer. Reduction of the reflected and scattered light results in improved resolution of developed images in photoresist. The developed images, when further processed into interconnecting conductors have improved definition, avoiding the additional process steps of applying a temporary dye or other light impervious layer.

492223

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