Method and device for analogue to digital conversion

H - Electricity – 03 – M

Patent

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Details

H03M 1/12 (2006.01) H03M 1/08 (2006.01)

Patent

CA 2316805

According to an embodiment of the invention, a parallel SC ADC (switched capacitor analogue-to-digital converter) is provided, comprising a passive sampling technique controlled by a global clock phase () to reduce the influence of the sampling phase skew. Since it does not require operational amplifiers for sampling, it is very suitable for high speed applications, and yet it can reduce the sampling-phase-skew-related distortion by 20-40dB in a high speed, parallel SC ADC.

Selon un mode de réalisation de l'invention, un convertisseur analogique/numérique à condensateur commuté (SC ADC) comprend un équipement d'échantillonnage passif commandé par une phase d'horloge mondiale (?) afin de réduire l'influence de l'obliquité de la phase d'échantillonnage. Ne nécessitant pas d'amplificateurs pour l'échantillonnage, non seulement il convient particulièrement aux applications grande vitesse mais aussi il permet de réduire de 20 à 40 dB la distorsion relative à l'obliquité de la phase d'échantillonnage dans un SC ADC une grande vitesse parallèle.

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