G - Physics – 06 – F
Patent
G - Physics
06
F
354/223, 354/67
G06F 11/10 (2006.01) H04L 1/00 (2006.01)
Patent
CA 1148660
ABSTRACT OF THE DISCLOSURE On carrying out conversion between a cyclic and a general code sequence, each consisting of a succession of normal code blocks and an additional or shorter code block, a zero bit series is hypothetically assumed before the additional code block. In an encoder for producing a cyclic code sequence, the zero bit series is hypothetically placed before the additional code block by cooperation of a timing control circuit and a divider. In a decoder, a counter for timing an additional cyclic code block starts counting while another counter is still counting to time a next preceding normal cyclic code block, whereby the zero bit series is assumed.
347495
Koga Keiichiro
Saga Ryokichi
Takimoto Yukio
Yasuda Yutaka
Kokusai Denshin Denwa Co. Ltd.
Nippon Electric Co. Ltd.
Smart & Biggar
LandOfFree
Method and device for carrying out conversion between a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for carrying out conversion between a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for carrying out conversion between a... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-476560