Method and device for generating check bits protecting a...

Details Method and device for generating check bits protecting a... Method and device for generating check bits protecting a...

G - Physics

06

F

354/223

G06F 11/10 (2006.01) F04C 29/02 (2006.01)

Patent

CA 1184307

ABSTRACT METHOD AND DEVICE FOR GENERATING CHECK BITS PROTECTING A DATA WORD Single error correction and double error detection with byte-wise generation of check bits. The individual bytes of the data word are successively applied via a byte selection logic to a bit selection logic comprising gates which pass on to a byte parity generation logic the data bits required in accordance with the code used. In this logic, one parity bit is generated to one respective switched data byte. The parity bits of the individual successively switched bytes are summed up in an accumulation logic, and supply the desired check bit after the last byte. The gates in the bit selection logic are controlled by a code implementing logic representing the respectively used check code. An error detecting and localizing logic detects the type of error, and defines the error location in case of a single error.

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