Method and device for synchronizing the receiver clock in a...

H - Electricity – 04 – L

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340/204

H04L 7/02 (2006.01) H04L 7/027 (2006.01) H04L 7/033 (2006.01) H04L 7/04 (2006.01)

Patent

CA 1057406

ABSTRACT A clock setting circuit is provided at a receiving modem for adjusting the phase of an timing signal defining the signal sampling instants. The received signal is filtered in two filters to derive a first signal having a phase ?1 and a frequency f1 equal to fc - 1/2T, fc being the carrier frequency and 1/T being the transmission baud rate, and a second signal having a phase ?2 and a frequency f2 equal to fc + 1/2T. The first and second derived signals are combined to derive an error signal indicative of the phase difference ?2 - ?1 which difference is used for adjusting the phase of a phase locked oscillator which provides the timing signal.

250715

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