Method and structure for controlling carrier lifetime in...

Details Method and structure for controlling carrier lifetime in... Method and structure for controlling carrier lifetime in...

H - Electricity

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L

356/77

H01L 21/76 (2006.01) H01L 21/265 (2006.01) H01L 27/092 (2006.01) H01L 29/08 (2006.01) H01L 29/167 (2006.01)

Patent

CA 1048653

METHOD AND STRUCTURE FOR CONTROLLING CARRIER LIFETIME IN SEMICONDUCTOR DEVICES Abstract of the Disclosure A method is presented for controlling the minority carrier lifetime in a semiconductor device by selectively implanting inert atoms such as helium, argon, neon, krypton, and xenon into specific regions of the device. The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

258550

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