Method and structure for interconnecting different...

Details Method and structure for interconnecting different... Method and structure for interconnecting different...

H - Electricity

01

L

H01L 23/522 (2006.01) H01L 21/768 (2006.01) H01L 23/532 (2006.01)

Patent

CA 2043172

A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

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