Method and system for generating parallel decodable low...

Details Method and system for generating parallel decodable low... Method and system for generating parallel decodable low...

H - Electricity

03

M

H03M 13/11 (2006.01) H04L 1/00 (2006.01) H04L 1/20 (2006.01)

Patent

CA 2472787

An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder (305) includes a memory (901, 1101) for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure (901, 1101). Additionally, the decoder (305) includes a parallel processors (903, 1103) accessing edge valves from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.

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