H - Electricity – 03 – M
Patent
H - Electricity
03
M
H03M 13/00 (2006.01) H03M 13/05 (2006.01) H03M 13/11 (2006.01) H03M 13/25 (2006.01) H03M 13/31 (2006.01) H04L 1/00 (2006.01)
Patent
CA 2454574
An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory (1501, 1503). The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.
L'invention concerne un procédé de décodage de signal ayant reçu un code à contrôle de parité faible densité. On extrait de la mémoire (1501, 1503) des valeurs marginales associées à une matrice de contrôle de parité structurée, pour la production du signal susmentionné. Ces valeurs spécifient la relation entre les noeuds de bit et les noeuds de contrôle. Elles sont enregistrées dans la mémoire selon un schéma préétabli permettant l'extraction simultanée d'une série de valeurs marginales. On fournit en sortie un signal décodé correspondant au signal codé considéré, sur la base des valeurs marginales extraites.
Cassagnol Bob
Eroz Mustafa
Lee Lin-Nan
Sun Feng-Wen
von Ancken Adam
Dtvg Licensing Inc.
Hughes Electronics Corporation
Sim & Mcburney
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