Method for configuration throughput of electronic circuits

G - Physics – 01 – R

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G01R 31/00 (2006.01) G06F 17/00 (2006.01)

Patent

CA 2533281

A system and method for maximizing the throughput of test and configuration in the manufacture of electronic circuits and systems. The system employs a tester having a flexible parallel test architecture (302) with expandable resources that can accommodate a selected number of units under test or UUTs (304.1, 304.2, 304.n). The parallel test architecture is configurable to accept separate banks or partitions of UUTs, thereby enabling the system to obtain an optimal or maximum achievable throughput of test and configuration for the UUTs. The system determines an optimal or maximum achievable throughput by calculating a desired number N of UUTs to be tested/configured in parallel. Testing or configuring this desired number of UUTs in parallel allows the handling time to be balanced with the test and configuration times, thereby resulting in the maximum achievable throughput.

L'invention concerne un système et un procédé destinés à maximiser la vitesse de test et de configuration dans la fabrication de circuits et de systèmes électroniques. Le système fait appel à un testeur possédant une architecture de test parallèle souple présentant des ressources extensibles pouvant prendre en charge un nombre sélectionné d'unités sous essai (UUT). L'architecture de test parallèle permet d'accepter des blocs ou des segments séparés des UUT, ce qui permet au système d'obtenir une vitesse de test et de configuration optimale ou maximale pour ces UUT. Le système détermine une vitesse optimale ou maximale par calcul d'un nombre souhaité N d'UUT à tester/configurer en parallèle. Le test ou la configuration de ce nombre souhaité d'UUT en parallèle permet d'équilibrer le temps de manutention avec les temps de test et de configuration, d'où l'obtention d'une vitesse maximale.

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