H - Electricity – 05 – K
Patent
H - Electricity
05
K
H05K 3/30 (2006.01) H01L 23/498 (2006.01) H05K 3/34 (2006.01)
Patent
CA 2217938
A method and apparatus is provided for connecting area grid array semiconductor chips (30) to a printed wire board (40). A compliant lead matrix (10) includes a carrier (12) and a plurality of conductive leads (14) arranged parallel to one another and secured relative to the carrier (12) in the form of a matrix. The method includes orienting a first side (16) of the lead matrix (12) to be aligned with a reciprocal matrix of conductive surface pads (36) on the area grid array semiconductor chip (30). First ends (20) of the leads are electrically connected to the conductive surface pads (36) of the area grid array chip (30). The second side (18) of the lead matrix (10) is oriented to be aligned with a reciprocal matrix of conductive surface pads (46) on a printed wire board (40). Second ends (22) of the leads (14) of the lead matrix (10) are electrically connected to the conductive surface pads (46) of the printed wire board (40) thereby establishing an electrical connection between the area grid array chip (30) and the printed wire board (40).
Bereskin & Parr Llp/s.e.n.c.r.l.,s.r.l.
Ceridian Corporation
General Dynamics Information Systems Inc.
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