Method for creating via hole in chip

Details Method for creating via hole in chip Method for creating via hole in chip

H - Electricity

01

L

H01L 21/26 (2006.01) H01L 21/71 (2006.01) H01L 21/768 (2006.01)

Patent

CA 2250795

A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip, and bombarding the chip(s) through the positioning holes of the transparent mask corresponding to the pre-formed pattern with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existent IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-patterned mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.

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