Method for defining submicron features in semiconductor devices

Details Method for defining submicron features in semiconductor devices Method for defining submicron features in semiconductor devices

H - Electricity

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H01L 21/32 (2006.01) H01L 21/033 (2006.01) H01L 21/265 (2006.01) H01L 21/266 (2006.01) H01L 21/302 (2006.01) H01L 29/872 (2006.01)

Patent

CA 1186809

METHOD FOR DEFINING SUBMICRON FEATURES IN SEMICONDUCTOR DEVICES Abstract A method for forming a guard zone is disclosed, suitable for a guard ring for a Schottky barrier diode or for a channel guard zone for protecting the channel inversion layer of an insulated gate field effect transistor. The method uses anistropic (straight-line) etching of a window in a thermally grown silicon dioxide layer on a silicon body combined with deposition of a metallic masking layer, such as aluminum, which is subject to a shadow effect of reduced thickness at a sidewall of the window. Slight etching of the metallic masking layer results in an aperture at the resulting edges of the masking layer located in the vicinity of the sidewall of the thermally grown oxide layer. Ions are then implanted with the body through the aperture, to form the guard zone.

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