Method for detecting an error bit in a multi-bit word

Details Method for detecting an error bit in a multi-bit word Method for detecting an error bit in a multi-bit word

G - Physics

06

F

354/224, 354/233

G06F 11/08 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1214882

A METHOD FOR DETECTING AN ERROR BIT IN A MULTI-BIT WORD Abstract of the Disclosure A method and apparatus for storing data in which the data is checked for an error without requiring the data to include an error correction code. Included in the system is a logic circuit for dividing a data word by a polynomial during the time the data word is being written into the primary memory unit resulting in the generation of a remainder which is stored in an auxiliary memory unit. When reading the data word from the primary memory unit, the data word is again divided by the same polynomial and the remainder compared with the remainder stored in the auxiliary memory unit. If the remainders match, no error as introduced during the storing of the data in the main memory unit. If the remainders do not match, an error is indicated. This system allows a data word to be stored in a main or primary memory unit without requiring the word to in- clude error correction bytes.

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