H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 21/28 (2006.01) H01L 21/308 (2006.01) H01L 21/338 (2006.01) H01L 21/78 (2006.01)
Patent
CA 1271850
METHOD FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH A SELF-ALIGNED GATE Abstract A method of fabricating a field-effect transistor is disclosed wherein only two masking steps are used in the development of the device. The semiconductor wafer used in the process has a non-alloyed contact at its top surface, that is, a contact which does not require alloying temperatures in excess of 200 degrees C. The first mask is used to create conventional mesa structures which isolate each individual field-effect transistor from its adjacent neighbors. A second mask is utilized to define the source and drain electrodes and also to create a gap through which the gate electrode structure is fabricated. By using a single mask for creation of both the source and drain electrodes and the gate structure, very close tolerances are obtained between the gate structure and thesource and drain regions.
554501
Cunningham John Edward
Schubert Erdmann Fred
Tsang Won Tien
American Telephone And Telegraph Company
Bell Telephone Laboratories Incorporated
Kirby Eades Gale Baker
LandOfFree
Method for fabricating a field-effect transistor with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a field-effect transistor with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a field-effect transistor with a... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1248321