B - Operations – Transporting – 05 – D
Patent
B - Operations, Transporting
05
D
356/199
B05D 5/12 (2006.01) G11C 11/34 (2006.01) G11C 16/04 (2006.01) H01L 21/28 (2006.01) H01L 29/792 (2006.01) H01L 45/00 (2006.01)
Patent
CA 1052009
METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE Abstract of the Disclosure An SI1I2M (semiconductor-insulator1-insulator2- metal) memory structure, containing a dopant such as tungsten or molybdenum concentrated in a region centered at the interface ("I1I2") between the I1 and I2 layers, is fabricated by depositing an oxide of the dopant, such as tungsten trioxide or molybdenum trioxide, on the I1 layer prior to fabricating the I2 layer. The oxide of the dopant can be advantageously deposited by means of reactive evaporation.
258791
Kahng Dawon
La Bate Ernest E.
Lepselter Martin P.
Ligenza Joseph R.
Na
Western Electric Company Incorporated
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