Method for fabricating igfet integrated circuits

Details Method for fabricating igfet integrated circuits Method for fabricating igfet integrated circuits

H - Electricity

01

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356/126, 356/30

H01L 21/50 (2006.01) H01L 21/768 (2006.01) H01L 21/8234 (2006.01) H01L 23/528 (2006.01) H01L 27/112 (2006.01)

Patent

CA 1143072

Law-1-1 - 18 - METHOD FOR FABRICATING IGFET INTEGRATED CIRCUITS Abstract of the Disclosure A rapid and systematic method for performing chip layout of a random-logic IGFET circuit includes steps for arranging the device features and interconnection features corresponding to the circuit in respective positions in an array of intersecting rows and columns. The method provides layouts of device and interconnection features having a high packing density and a high degree of order and regularity to facilitate checking for layout errors,

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