Method for fabricating improved complementary metal oxide...

Details Method for fabricating improved complementary metal oxide... Method for fabricating improved complementary metal oxide...

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H01L 21/28 (2006.01) H01L 21/02 (2006.01) H01L 21/8238 (2006.01) H01L 29/49 (2006.01)

Patent

CA 1166361

METHOD FOR FABRICATING IMPROVED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES Abstract of the Disclosure Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single con- ductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffu- sion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity. The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the con- ductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resis- tors to protect them during the high conductivity doping of the conductors.

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