H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 27/08 (2006.01) H01L 21/336 (2006.01) H01L 21/762 (2006.01) H01L 27/112 (2006.01) H01L 29/76 (2006.01) H01L 29/78 (2006.01)
Patent
CA 1131796
Abstract of the Disclosure A method for fabricating an integrated circuit semiconduct- or device comprised of an array of MOSFET elements having self- aligned or self-registered connections with conductive interconnect lines. The method involves the formation on a substrate of a thick oxide insulation layer surrounding openings therein for the MOSFET elements. A gate electrode within each opening is utilized to pro- vide self-registered source and drain regions and is covered on all sides and on its top surface with a dielectric layer. After source-drain diffusions a relatively thin dielectric protective layer is initially applied to the entire chip prior to the appli- cation of an upper insulative layer. When oversized windows are etched in the upper insulative layer the protective layer prevents overetching of the gate dielectric layer thus preventing shorts or leaks between conductive and active areas and providing self- aligned contacts with minimum spacing from adjacent conductive areas. With the present method the additional internal protection is provided for in MOS devices with source-drain regions formed either by diffusion or ion implantation.
339798
American Microsystems Inc.
Gowling Lafleur Henderson Llp
LandOfFree
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