H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 21/302 (2006.01) H01L 21/027 (2006.01) H01L 21/033 (2006.01) H01L 29/812 (2006.01)
Patent
CA 1126876
METHOD FOR FABRICATING SELF-ALIGNED HIGH RESOLUTION NON PLANAR DEVICES EMPLOYING LOW RESOLUTION REGISTRATION Abstract A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabri- cate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device YO978-012 elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isola- tion and interconnection of single devices into large circuits on a semiconductor chip. YO978-012
345149
Gaensslen Fritz H.
Spiller Eberhard A.
International Business Machines Corporation
Na
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