H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/130
H01L 21/22 (2006.01) H01L 21/00 (2006.01) H01L 21/033 (2006.01) H01L 21/266 (2006.01)
Patent
CA 1087322
Abstract of the Disclosure A method for fabricating semiconductor devices from a semiconductor body having a planar surface by forming on the surface a layer of protective material which is to be utilized as a mask. A plurality of windows are formed simultaneously in the layer of protective material to expose said surface to permit the subsequent formation of isolation regions, base regions and collector contact regions in the semiconductor body. Ion implanta- tion is carried out at low temperatures through certain of the openings while covering the other openings to form the respective regions thereby eliminating the necessity for mask to mask tolerance requirements and tolerances required for thermal diffusions.
210560
Marley James A.
Polata Bohumil
Signetics Corporation
Smart & Biggar
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