Method for fabricating transistor structures having very...

Details Method for fabricating transistor structures having very... Method for fabricating transistor structures having very...

H - Electricity

01

J

356/128

H01J 17/00 (2006.01) H01L 21/033 (2006.01) H01L 21/265 (2006.01) H01L 21/336 (2006.01) H01L 29/10 (2006.01)

Patent

CA 1115855

ABSTRACT A method, including a sequence of process steps, for fabri- cating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process stop and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value. Y0977-057

325550

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