Method for forming a planarized integrated circuit

Details Method for forming a planarized integrated circuit Method for forming a planarized integrated circuit

H - Electricity

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H01L 21/76 (2006.01) H01L 21/3105 (2006.01) H01L 21/316 (2006.01) H01L 21/768 (2006.01) H01L 23/29 (2006.01) H01L 23/31 (2006.01) H01L 27/00 (2006.01)

Patent

CA 1166763

FI 9-81-045 METHOD FOR FORMING A PLANARIZED INTEGRATED CIRCUIT Abstract A method is given for forming a planarized integ- rated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated cir- cuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy has been formed on the principal surface of the product. A glass layer is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approx- imates that silicon and has a softening temperature of less than about 1200°C. The thermal coefficient of expansion approximates that of silicon to reduce stress problems in the integrated circuit structure. The relatively low softening temperature is required for the next step of heating the structure to cause the flow of glass on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass down to the device elements of the integrated circuit. The inter- connection metallurgy is formed over the surface of the glass and through the openings of the glass to inter- connect the device elements of the integrated circuit. The glass may be deposited by various methods which include the sedimentation methods of spraying, cen- trifuging and spin-on plus sputtering or evaporation methods.

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