Method for forming dense multilevel interconnection...

Details Method for forming dense multilevel interconnection... Method for forming dense multilevel interconnection...

H - Electricity

05

K

96/249

H05K 3/07 (2006.01) H01L 21/027 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1168916

ABSTRACT A method for providing high density multiple level metallurgy for integrated circuit devices in which a relatively thin layer of plasma produced silicon nitride is deposited over a first level of interconnection metallurgy formed on a layer of silicon oxide. Overlap via holes are etched in the nitride layer followed by deposition of a thicker layer of polyimide forming polymer. A second set of via holes larger than the first are provided in the polymer layer and a second layer of interconnection metallurgy is then deposited by a lift-off deposition technique. BU9-79-015

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