Method for generating a correction signal in a digital clock...

H - Electricity – 04 – L

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328/87

H04L 7/02 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1292288

Abstract Disclosed is a method for generating a correction signal in a digital clock recovery device. A digital clock recovery system according to a prior proposal contains in a phase sensor a delay device. This cannot be implemented with the required accuracy in integrated circuit technology. It is therefore intended to develop a method which does not need any delay device for its implementation. In this method, the phase sensor does not compare the phase relationship of the active edges of the pulses of a digital signal with a first auxiliary data clock which acts as clock recovered from the digital signal. Instead, the phase sensor compares the phase relationship of the active edges of the pulses of the digital signal and of a second auxiliary data clock which exhibits a defined phase difference with respect to the first auxiliary data clock. If the comparison does not result in a phase difference, a correction signal is generated which causes a phase correction of both auxiliary data clocks producing the defined phase difference. Digital clock recovery devices are used in digital signal multiplexing devices and distributor multiplexors between, in particular, higher levels of a digital signal hierarchy.

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