Method for generating electronic circuits

G - Physics – 06 – F

Patent

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G06F 17/50 (2006.01)

Patent

CA 2450627

The present invention relates to a method for obtaining electronic circuits wherein the design steps (100) constituted by a first development and testing cycle (200), of the functional type, and a second development and testing cycle (300), of the architectural type, are managed using, as inputs, for both cycles (200 and 300) the same configuration files (140) and stimuli (150) and generating, at the output, results having equivalent (230, 330) and comparable (333) formats. Thanks to these characteristics, it is possible to conduct in integrated fashion functional tests (220) and architectural tests (320) on corresponding functional and architectural models of electronic circuits and verify the perfect correspondence between the different types of models as the configurations files (140) and stimuli (150) vary.

La présente invention concerne un procédé de fabrication de circuits électroniques dans lequel les étapes (100) de conception constituées par un premier cycle (200) de développement et d'essai de type fonctionnel, et un second cycle (300) de développement et d'essai de type architectural, sont gérées grâce à l'utilisation comme entrées, pour les deux cycles (200 et 300) des mêmes fichiers (140) de configuration et stimuli (150), et par génération à la sortie de résultats présentant des formats équivalents (230, 330) et comparables (333). Grâce à ces caractéristiques, il est possible d'exécuter des tests fonctionnels (220) et des tests architecturaux (320) de manière intégrée sur des modèles fonctionnels et architecturaux correspondants de circuits électroniques, et de vérifier la parfaite correspondance entre les différents types de modèles lorsques les fichiers (140) de configuration et stimuli (150) varient.

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