Method for improved interrupt handling within a microprocessor

G - Physics – 06 – F

Patent

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G06F 9/38 (2006.01) G06F 9/48 (2006.01)

Patent

CA 2305165

A method and apparatus for processing interrupts received by a processor during the processing of an instruction set by a processing pipeline is disclosed. Initially, an interrupt associated with an interrupt service routine is received during processing of the instruction set. In response to receipt of the interrupt, an interrupt instruction register is accessed containing at least one interrupt instruction associated with the interrupt service routine. The at least one interrupt instruction is inserted directly into the processing pipeline of the processor. The inserted instruction is then executed and control returns back to processing of the original instruction set after execution of at least one interrupt instruction.

L'invention concerne un procédé et un appareil permettant de traiter des interruptions (30) reçues par un processeur (45) pendant le traitement d'un ensemble d'instructions par pipeline de traitement (55). Initialement, une interruption (30) associée à une routine de service de traitement d'interruptions est reçue pendant le traitement d'un ensemble d'instructions. En réaction à la réception de l'interruption (30), on accède à un registre d'instruction d'interruption (50) contenant au moins une instruction d'interruption associée à la routine de service de traitement d'interruptions. La ou les instruction(s) d'interruptions sont insérées directement dans le pipeline de traitement (55) du processeur (45). L'instruction insérée est ensuite exécutée et elle commande des retours au traitement de l'ensemble d'instructions d'origine après exécution d'au moins une instruction d'interruption.

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