Method for increased input isolation in sampling gates

Details Method for increased input isolation in sampling gates Method for increased input isolation in sampling gates

G - Physics

11

C

G11C 27/02 (2006.01)

Patent

CA 2395895

A method for achieving increased input isolation in sampling gates is taught herein. The increased input isolation is accomplished by providing identical isolation paths from the primary (1,2) and isolation (3,4) differential inputs to the hold capacitor (17) when in hold mode (22). The method is general in nature and can be applied to a wide range of sampling gate architectures and technologies.

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