Method for inserting test points for full- and partial-scan...

Details Method for inserting test points for full- and partial-scan... Method for inserting test points for full- and partial-scan...

G - Physics

01

R

G01R 31/3177 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2187466

Test points (20, 24) placed at selected nodes (16) within a circuit ( 10) based on a cost function that accounts for (a) the global improvement in testability and (b) the penalty in circuit performance associated with propagation delays attributable to such test points. By accounting for both the global impact on testability and circuit performance degradation, the cost function maximizes fault coverage while achieving nearly minimal impairment of circuit performance.

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