Method for manufacture of integrated semiconductor circuits,...

Details Method for manufacture of integrated semiconductor circuits,... Method for manufacture of integrated semiconductor circuits,...

H - Electricity

01

L

356/197

H01L 21/28 (2006.01) H01L 21/20 (2006.01) H01L 21/339 (2006.01) H01L 21/8234 (2006.01)

Patent

CA 1163730

ABSTRACT OF THE DISCLOSURE In an exemplary embodiment, a first polysilicon layer is provided with a SiO2 mask, and the first polysilicon layer is etched away under the SiO2 mask to produce SiO2 overhangs of a lateral extent corresponding to about twice the edge position error (+s). Then when second polysilicon layers are produced by means of chemical vapor deposition (CVD), to occupy the cavities under the SiO2 overhangs, the desired nonoverlapping poly-Si-2 electrodes result after definition of those poly-Si-2 electrodes by known lithographical techniques.

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