Method for manufacture of integrated semiconductor circuits,...

Details Method for manufacture of integrated semiconductor circuits,... Method for manufacture of integrated semiconductor circuits,...

H - Electricity

01

L

356/197

H01L 21/28 (2006.01) H01L 21/339 (2006.01) H01L 21/8234 (2006.01)

Patent

CA 1159967

ABSTRACT OF THE DISCLOSURE In an exemplary embodiment, after underetching a first poly- silicon layer beneath spaced SiO2 cover layers to produce pairs of confronting SiO2 overhangs with gaps therebetween, and providing an insulating layer at the end faces of the spaced poly-Si-1 electrodes formed from the first polysilicon layer, a second polysilicon layer is produced by chemical vapor deposition (CVD) so as to fill the cavities beneath the SiO2 overhangs via the gaps between each pair of confronting overhangs. The second polysilicon layer is then etched away so as to leave intervening self-adjusting, nonoverlapping poly-Si-2 electrodes formed from the second polysilicon layer with surfaces terminating for example slightly below the upper surfaces of the SiO2 cover layers. For a center-to-center spacing of poly-Si-1 electrodes of six microns, the SiO2 overhangs may have an extent (e.g. .7 microns) about equal to the electrode layer thickness (e.g. .8 microns).

361133

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