H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149, 356/172
H01L 29/78 (2006.01) H01L 21/033 (2006.01) H01L 21/225 (2006.01) H01L 21/336 (2006.01)
Patent
CA 1198226
- 21 - METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Abstract A method for manufacturing an IGFET device which provides IGFETs having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The thickness of the source layer and the conditions of oxidation are such that the rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature and that during the oxidation time, the arsenic in the source layer diffuses into the silicon to form extremely shallow source and drain regions.
427418
Kinsbron Eliezer
Lynch William T.
Kirby Eades Gale Baker
Western Electric Company Incorporated
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