Method for manufacturing an integrated circuit device

Details Method for manufacturing an integrated circuit device Method for manufacturing an integrated circuit device

H - Electricity

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H01L 21/78 (2006.01) H01L 21/48 (2006.01) H01L 21/58 (2006.01) H01L 21/60 (2006.01) H01L 23/14 (2006.01) H01L 23/482 (2006.01)

Patent

CA 1205578

-1- Abstract: An integrated circuit 14 having an active circuit 19 is formed on a circuit wafer 10. A moat 18 in the field oxide 20 surrounds the active circuit 19. Metallic conductor 30 passes from a location on the active circuit 19 over the moat 18 to a contact area 22. The wafer 10 is covered with a photoshaped silicon nitride layer 18, and a support wafer 40 is secured with adhesive 46 to the circuit side of the circuit wafer 10. The circuit wafer 10 is photoshaped to expose the metallic conductor 30 at the contact area 22, and the contact area 22 is prepared with multiple metal layers 62, 66, 70 for connection to external wiring.

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