H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 29/78 (2006.01) H01L 21/336 (2006.01) H01L 29/423 (2006.01)
Patent
CA 1306313
ABSTRACT One method for manufacturing double-diffused metal-oxide-semiconductor field effect transistor (DMOSFET) devices begins with forming an insulating layer having openings in its top surface on a semiconductor wafer. Channel regions, well regions and source regions are then formed by two stage diffusions of impurity materials through the openings. The impurity materials are respect- ively of a different conductivity type from and the same conductivity type as the wafer. Next, masks are provided on the surface area over the drain regions and the source electrode regions that are to be connected to the well regions and source regions. An impurity material of the same conductivity type as the wafer is introduced into the channel regions by ion-implantation. Gate, source and drain electrodes are then formed. The parameters in this process can be adjusted to allow the threshold voltage to be controlled to achieve a depletion type device. The carrier concentration in the channel regions of the result- ing device is low compared to the carrier concentration in other parts of the well regions. The result is a depletion type device with a high breakdown voltage.
587805
Akiyama Sigeo
Nobe Takeshi
Suzumura Masahiko
Matsushita Electric Works Ltd.
Oyen Wiggs Green & Mutala Llp
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