Method for manufacturing vlsi complementary mos field effect...

Details Method for manufacturing vlsi complementary mos field effect... Method for manufacturing vlsi complementary mos field effect...

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H01L 21/82 (2006.01) H01L 21/265 (2006.01) H01L 21/28 (2006.01) H01L 21/8238 (2006.01) H01L 27/06 (2006.01)

Patent

CA 1187209

ABSTRACT OF THE DISCLOSURE Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations occur with only one mask. This mask, which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors. The source/drain implant- ation for the p-channel transistors occurs without a mask and the oxide layer thickness, d6, over the source/drain regions of the n-chan- nel transistors functions as a masking layer. An advantage of this process sequence is that switched capacitor structures can be simul- taneously produced whereby the oxide layer thickness, d4, over the polysilicon-1 level determines the thickness of the insulating layer, dcox, of the capacitor structures. This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

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