H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/129
H01L 21/76 (2006.01) H01L 21/033 (2006.01) H01L 21/308 (2006.01) H01L 21/762 (2006.01) H01L 21/8238 (2006.01) H01L 27/092 (2006.01)
Patent
CA 1287692
ABSTRACT OF THE DISCLOSURE A double well CMOS process wherein the wells are separated by insulating trenches introduced into a semiconductor substrate, the position of the insulating trench along the isotropic under-etching in a silicon oxide layer employed together with a silicon nitride layer used as a masking layer in the implantation of the well which is first implanted. The trench itself is produced by anisotropic etching with silicon oxide masks used in the well implantations as etching masks. The trench width is defined with the isotropic etching and the trench depth is defined by the anisotropic etching. In this method, both well implanatations and the trench etching are carried out with only one photo-technique. The implantation of the second well and the trench etching are self-adjusting. As a result, minimum spacings between the active zones are provided, and a space saving design is possible. The method is used in LSI CMOS processes.
573561
Mazure-Espejo Carols-A.
Neppl Franz
Zeller Christoph
Fetherstonhaugh & Co.
Mazure-Espejo Carols-A.
Neppl Franz
Zeller Christoph
LandOfFree
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