Method for processing atm cells in bidirectional data streams

Details Method for processing atm cells in bidirectional data streams Method for processing atm cells in bidirectional data streams

H - Electricity

04

L

H04L 12/56 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2295221

The invention relates to a method for processing ATM cells in upstream and downstream bidirectional data flows in an ATM component in which the processing speed is greater than the mean cell rate and empty cycles without ATM cells are present in the cell flow. To allow for two-way alternate processing of upward and downward cells, the processing logic (VAL) of the component (BST) issues requests (EC up req, EC down req) for empty cycles upstream and downstream to an empty- cycle control unit (LZS) so as to obtain processing time. The cells of the downstream data flow can be stored and released separately in a buffer (BUF) so that in this way empty cycles can be generated downstream. Should an empty cycle occur, an upstream request for empty cycles (EC up req) is processed as a priority in relation to a simultaneous downstream request. In case of a downstream empty cycle request (EC down req) an empty cycle is released with a delay of one cycle period if there is a simultaneous upstream request. If this is not the case, it is released immediately.

L'invention concerne un procédé de traitement de cellules MTA dans des flux de données bidirectionnels ascendants et descendants dans un circuit MTA où la vitesse de traitement est supérieure au taux de cellules moyen et où des cycles vides sans cellules MTA se présentent dans le flux de cellules. Pour permettre un traitement alterné de cellules ascendantes ou descendantes, la logique de traitement (VAL) du circuit (BST) envoie à une commande de cycles vides (LZS) des demandes ascendantes et descendantes (EC up req, EC down req) de cycles vides afin d'obtenir du temps de traitement. Les cellules du flux de données descendant peuvent être empilées dans une mémoire tampon (BUF) et libérées séparément, ce qui permet de générer des cycles vides descendants. Une demande de cycle vide ascendante (EC up req) est traitée prioritairement par rapport à une demande descendante simultanée lorsqu'un cycle vide se présente. Pour une demande de cycle libre descendante (EC down req) en revanche, un cycle libre est libéré avec un retard d'une longueur de cycle si une demande ascendante est simultanément présente; sinon, il est libéré immédiatement.

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