Method for producing vlsi complementary mos field effect...

Details Method for producing vlsi complementary mos field effect... Method for producing vlsi complementary mos field effect...

H - Electricity

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H01L 21/28 (2006.01) H01L 21/265 (2006.01) H01L 21/762 (2006.01) H01L 21/8238 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1187210

ABSTRACT OF THE DISCLOSURE Analog or digital MOS circuits in VLSI technology are produced by a method in which the manufacture of two troughs occurs with only one mask used in production of the p-trough, The n-trough is formed by a surface-wide implantation of an ion selected from a group consisting of P, As and Sb. The channel implantation of the p-transistors occurs simultaneously. The field and channel implantation of the n- channel transistors is carried out with a silicon nitride mask, i.e., a LOCOS mask, and a double boron implantation. The field implantation of the p-channel transistors is carried out with arsenic. Advantages of this process sequence include reduction of parasistic edge capaci- tances at the source/drain edges with fewer masking steps.

410214

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