H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/126, 356/128
H01L 21/76 (2006.01) H01L 21/00 (2006.01) H01L 21/306 (2006.01) H01L 21/308 (2006.01) H01L 21/311 (2006.01) H01L 21/32 (2006.01) H01L 21/762 (2006.01)
Patent
CA 1053378
METHOD AND DEVICE FOR REDUCING SIDEWALL CONDUCTION IN RECESSED OXIDE FET ARRAYS Abstract of the Disclosure Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistor (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide thereon. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a <100> oriented p-conductivity type substrate.
224582
Dennard Robert H.
Rideout Vincent L.
Walker Edward J.
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