Method for simultaneously manufacturing n-channel mos...

Details Method for simultaneously manufacturing n-channel mos... Method for simultaneously manufacturing n-channel mos...

H - Electricity

01

L

356/127

H01L 21/70 (2006.01) H01L 21/8249 (2006.01)

Patent

CA 2018089

A METHOD FOR SIMULTANEOUSLY MANUFACTURING N-CHANNEL MOS TRANSISTORS AND VERTICAL PNP BIPOLAR TRANSISTORS ABSTRACT OF THE DISCLOSURE A manufacturing method of an integrated circuit comprising N-channel MOS transistors and vertical PNP bipolar transistors comprises the following successive steps, carried out after forming the MOS transistor gates: implanting an N- region (44; 45, 46) and annealing; implanting an N+ region (55; 53. 54) except at the place where will be formed the emitter of the bipolar transistor, and annealing; implanting a P+ region (61) at the place where it is desired to form the bipolar transistor, and annealing; the implantations and annealing of the P+ and N+ regions being carried out so that there remains a portion of the layer resulting from the N- implantation under each of those regions.

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