Method for testability analysis and test point insertion at...

Details Method for testability analysis and test point insertion at... Method for testability analysis and test point insertion at...

G - Physics

06

F

G06F 17/50 (2006.01) G01R 31/3185 (2006.01)

Patent

CA 2273628

A method of producing a synthesizable RT-Level VHDL specification for input to a synthesis tool to generate a gate-level circuit having testability enhancement, the method comprising the steps of developing a synthesizable RT-Level VHDL specification representative of said circuit, analyzing said VHDL specification to produce a VHDL Intermediate Format (VIF) representation; transforming said VIF representation into a Directed Acyclic Graph (DAG); performing testability analysis on said Directed Acyclic Graph by computing and propagating Testability Measures (TMs) forward and backward through VHDL statements of said Directed Acyclic Graph; identifying the bits of each signals/variables on which faults are hard to detect; and performing test point insertion in said specification at the RT-Level by adding new VHDL test statements to improve testability.

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