Method for testing cryptographic circuits, secured...

G - Physics – 06 – F

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G06F 21/00 (2006.01) G01R 31/317 (2006.01)

Patent

CA 2716143

The present invention relates to a method for testing cryptography circuits. It also relates to a secure cryptography circuit capable of being tested. The cryptography circuit comprising registers and logic gates (211, 212, 213, 214), a test according to the invention performs a differential power analysis (DPA) on the registers of the circuit. A cryptography circuit being secure and comprising a first half-circuit (211, 214) associated with a second half-circuit (212, 213) operating in complementary logic, the electric power supply (Vdd1, 23, 25) of the first half--circuit is separated from the electric power supply (Vdd2, 24) of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two power supplies being combined into one and the same electric power supply after the test.

La présente invention concerne un procédé de test de circuits de cryptographie. Elle concerne également un circuit de cryptographie sécurisé apte à être testé. Le circuit de cryptographie comportant des registres et des portes logiques (211, 212, 213, 214) un test selon l'invention effectue une analyse différentielle de consommation (DPA) sur les registres du circuit. Un circuit de cryptographie étant sécurisé et comportant un premier demi-circuit (211, 214) associé à un deuxième demi-circuit (212, 213) fonctionnant en logique complémentaire, l'alimentation électrique (Vdd1, 23, 25) du premier demi-circuit est dissociée de l'alimentation électrique (Vdd2, 24) du deuxième demi-circuit, l'analyse différentielle de consommation étant réalisée parallèlement sur chaque demi-circuit, les deux alimentations étant regroupées en une même alimentation électrique après le test.

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