Method for the construction of vertical power transistors...

Details Method for the construction of vertical power transistors... Method for the construction of vertical power transistors...

G - Physics

06

F

G06F 17/50 (2006.01)

Patent

CA 2587426

Method and system for designing a vertical MOS power transistor with specified design output. The method comprises the composition of a layout for the vertical MOS power transistor as a combination of at least partly different layout sections, each with known design data with at least one first layout section with a known number of individual transistors and the fixing of the specific design output by means of the known design data and the number of applied layout sections.

L'invention concerne un procédé et un système de conception d'un transistor MOS de puissance vertical à puissance théorique spécifique. Ledit procédé consiste à combiner une topologie du transistor MOS de puissance vertical comme association d'éléments de topologie, au moins partiellement différents, à données de conception connues avec au moins un premier élément de topologie, présentant un nombre prédéfini de cellules de transistor individuelles, et à régler la puissance théorique spécifique à l'aide des données de conception connues et du nombre d'éléments de topologie utilisés.

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