Method for the manufacture of gate electrodes formed of...

Details Method for the manufacture of gate electrodes formed of... Method for the manufacture of gate electrodes formed of...

H - Electricity

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356/125

H01L 21/28 (2006.01) H01L 21/3215 (2006.01) H01L 21/8238 (2006.01) H01L 29/49 (2006.01)

Patent

CA 1228681

ABSTRACT OF THE DISCLOSURE A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n+- and p+-polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.

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