Method for the manufacture of integrated mos-filed effect...

Details Method for the manufacture of integrated mos-filed effect... Method for the manufacture of integrated mos-filed effect...

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H01L 21/768 (2006.01) H01L 21/28 (2006.01) H01L 21/285 (2006.01) H01L 21/336 (2006.01) H01L 29/45 (2006.01) H01L 29/49 (2006.01)

Patent

CA 1203642

ABSTRACT OF THE DISCLOSURE A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

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