Method for the manufacture of lsi complementary mos field...

Details Method for the manufacture of lsi complementary mos field... Method for the manufacture of lsi complementary mos field...

H - Electricity

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356/125

H01L 21/82 (2006.01) H01L 21/8238 (2006.01) H01L 27/08 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1257710

ABSTRACT OF THE DISCLOSURE A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up strength of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by outward diffusion into the epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n+/p+ spacing, and thus achieves a higher packing density with improved latch-up strength.

539065

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