Method of and apparatus for generating a pseudorandom noise...

G - Physics – 06 – F

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G06F 1/02 (2006.01) G06F 7/58 (2006.01) H04L 9/22 (2006.01)

Patent

CA 2210211

An augmenting circuit (153) augments an embedded PN sequence of 2N-1 chips generated by an N-bit LSSR (111) to provide an augmented PN sequence of 2N chips and an augmented PN sequence of 2N chips shifted by D chips. The augmenting circuit comprises a N-bit counter (123) that counts a plurality of clock bits. The N-bit counter provides a pre-carry signal that changes state when the counter's index equals a predetermined value and provides a value of the N-k most-significant-bits (MSB) of the index. A logic circuit (107,119) receives the plurality of clock bits and responds to the pre-carry signal to gate the plurality of clock bits. A comparator (135) receives the value of the N-k MSB and a threshold value to output a select signal that controls a multiplexer (139).

Circuit d'augmentation (153) permettant d'augmenter une séquence de bruits pseudo-aléatoires (PN) intégrée de 2N-1 éléments générée par un LSSR de N-bits (111) afin de produire une séquence de PN augmentée de 2N éléments et une séquence de PN augmentée de 2N éléments décalée de D éléments. Le circuit d'augmentation comprend un compteur de N-bits (123) qui compte un certain nombre de bits d'horloge. Le compteur de N-bits produit un signal de pré-report qui change d'état lorsque l'indice du compteur correspond à une valeur prédéterminée et produit une valeur des N-k bits de poids fort (MSB) de l'indice. Un circuit logique (107, 119) reçoit lesdits bits d'horloge et répond au signal de pré-report afin de bloquer/débloquer lesdits bits d'horloge. Un comparateur (135) reçoit la valeur des N-k MSB et une valeur de seuil afin de produire en sortie une signal de sélection qui commande un multiplexeur (139).

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