G - Physics – 11 – C
Patent
G - Physics
11
C
354/222
G11C 29/00 (2006.01) G11C 29/02 (2006.01) G11C 29/10 (2006.01) G11C 29/18 (2006.01) G11C 29/56 (2006.01) H03K 5/19 (2006.01)
Patent
CA 1051556
ABSTRACT: The invention provides a compact test sequence for testing integrated memories. First, all storage positions are filled with the information "O". subse- quently, in a given order of the addresses the information "O" written for each address is read; immediately there- after a "1" is written which is immediately tested thereafter by reading again. When the last address of the said order is reached, the "1" is read in the same order for each address, and subsequently a "O" is written, which is finally tested by reading again. When the last address is reached, all addresses are read in the reverse order, and a "even" is written which is tested again. When the first address is reached, all addresses are read, filled with a "O" and tested. This process is repeated, for example, as many times as there are bits in the address, the significance of the address bits being modified in order to form the said order for example, by cyclic rotation. For example, in the first cycle the order may be the normal order of successive addresses, whilst in the second cycle first all "even" and then all "odd" addreses are treated etc. If there are N address bits, N cycles will be sufficient, and in the case of one bit per address there will be (12N + 1)2N read and write operations. This number must possibly be mul- tiplied by the number of storage bits per address po- sition. The number of storage operations remains sub- stantially smaller than in many test methods offer- ing corresponding quality.
242285
de Jonge Jan H.
Smulders Adrianus J.
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