Method of assembling tab bonded semiconductor chip package

H - Electricity – 01 – L

Patent

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H01L 21/60 (2006.01) H01L 21/50 (2006.01) H01L 23/04 (2006.01) H01L 23/36 (2006.01) H01L 23/48 (2006.01) H01L 23/495 (2006.01)

Patent

CA 1297597

83-465 PATENTS ABSTRACT OF THE DISCLOSURE A package for housing fabricated semiconductor chips is disclosed. The package has ceramic base with a raised outer shelf extending around its periphery. The outer shelf defines a space in the package where the chip is seated. A lead frame with a number of individual conductive leads is disposed over the outer shelf. A section of tape automated bonding tape is used to provide electrical connections between bonding points on the chip and the lead frame leads; the tape automated bonding tape carries a number of conductive leads each of said leads having an inner lead portion attached to a chip bonding point, and an outer lead portion attached to a lead frame lead. A frame is secured over the base outer shelf so the lead frame is embedded therebetween. A lid is secured over the frame to completely enclose the chip within the package. An adhesive that can be cured at a low temperature so as to not delaminate the tape automated bonding tape, is used to secure the frame and lead frame to the base, secure the chip in the space and secure the lid to the frame.

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